(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of rerouting semiconductor device Input/Output (I/O) connections. This leads to a method of improved logistics control, whereby a variety of Integrated Circuit packages of different dimensions can be handled. The rerouting of the I/O pads of semiconductor devices is achieved by providing an extra layer of polyimide over which relocated pads are created, the relocated pads are attached to the standard pads on a semiconductor die using wire bonding.
(2) Description of the Prior Art
The design and manufacturing of semiconductor devices requires the cooperative application of a number of divers technologies. A large number of these technologies are aimed at creating semiconductor devices, other technical disciplines are aimed at packaging the semiconductor devices after these devices have been created. A major trend in the semiconductor technology has for many years been the reduction in device dimensions, which provides for improved device performance. Reduction in device dimension leads as a natural extension to increased device densities. From this it follows that the interconnection of semiconductor devices, which contain significantly increased functionality while the device is concurrently reduced in size, is a major challenge in the art. This challenge is addressed by the packaging of semiconductor devices, whereby changes in devices are closely followed by changes in the packages in which these devices are mounted. One of the key considerations in the package design is the accessibility of the semiconductor device or, to express this another way, the Input/Output (I/O) capability of the package after one or more devices have been mounted in the package.
The process of packaging semiconductor devices typically starts with a substrate that is ceramic or plastic based, the devices are mounted on the surface of the substrate while layers of interconnect lines and vias are formed that connect the devices to its surrounding circuitry. Many different approaches are known and have been used for the mounting and interconnecting of multiple semiconductor devices, such as Dual-In-Line packages (DIP's), Pin Grid Arrays (PGA's), Plastic Leaded Chip Carriers (PLCC's) and Quad Flat Packages (QFP's). Multi layer structures have further been used to connect physically closely spaced integrated circuits with each other. Using these techniques, a single substrate serves as an interconnect medium, multiple chips are connected to the interconnect medium forming a device package with high packaging density and dense chip wiring. The chip wiring contains layers of interconnect metal that are interconnected with interconnect vias, layers of dielectric (such as polyimide) or insulating layers separate metal layers that make up the interconnect network and the vias and contact points that establish connections between the interconnect networks. The design of overlying and closely spaced interconnect lines is subject to strict rules of design that are aimed at improving package performance despite the high density packaging that is used. For instance, electrical interference between adjacent lines is minimized or avoided by creating interconnect lines for primary signals that intersect under 90 degree angles. Surface planarity must be maintained throughout the construction of multi-layer chip packages due to requirements of photolithography and package reliability. Many of the patterned layers within a layered structure form the base for overlying layers, lack of planarity can therefore have a multiplying effect on overlying layers.
The Quad Flat Package (QFP) has been created to achieve high pin count integrated packages with various point configurations. The pin I/O connections for these packages are typically established by closely spaced leads distributed along the four edges of the flat package. This limits the I/O count of the packages and therefore the usefulness of the QFP. The Bail Grid Array (BGA) package has been created whereby the I/O connects for the package are distributed around the periphery of the package and over the complete bottom of the package. The BGA package can therefore support more I/O points and provides a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
Another packaging concept is realized with the use of so-called flip chips. The flip chip is a semiconductor device that has conductive layers formed on its top surface, external electrical interconnects can be made to these conductive layers by wire boning selected points of the conductive layers to surrounding circuitry or interconnect lines. For instance, if CMOS devices are created using the flip chip concept, the VSS and VDD voltage that is needed for the operation of the device can be supplied through selected vias or contact pads in the top surface of the CMOS device. The top surface of the flip chip is further provided with so-called solder bumps. At the time of assembly of the flip chip, the chip is turned over (flipped over) so that the solder bumps are now facing downwards and toward the circuit board, typically a printed circuit board, on which the flip chip is to be mounted. The solder bumps (on the now downward facing surface of the flip chip) are aligned with and brought into contact with contact pads that are for this purpose created in the top surface of the circuit board. The solder bumps are, by means of solder reflow or any other means, connected to the contact pads of the circuit board.
In advanced microelectronic packaging of integrated circuits, particularly high-speed, high-density packaging for main frame computer applications, the chips are often mounted on multi-chip modules such as polyimide substrates, which contain buried wiring patterns to conduct electrical signals between various chips. These modules usually contain multiple layers of interconnect metallization separated by alternating layers of an isolating dielectric whose function is to serve as electrical isolation between the metal features. Any conductor material that is used in a multilevel interconnect has to satisfy certain essential requirements such as low resistively, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
It is clear from the above that, in a typical semiconductor device package, the device can be mounted or positioned in a package and further connected to interconnect lines of the device package by bond wires or solder bumps. For this purpose the to be packaged semiconductor device is provided with pads (bond pads) that are, for ease of access, mounted around the perimeter of the device. Wires are connected from the bond pads to the supporting circuit board or to other means of providing interconnect lines such as Tape Automated Bonding (TAB) device packages. For the packaging techniques that are used, the requirements that are imposed on the method of packaging universally address the same concerns and limitations. These concerns and limitations are imposed by considerations of the (type of) device that is being packaged, by the number of the devices that are mounted within one package, by electrical performance of the individual devices in the package and the impact of the package on the electrical performance, by thermal considerations and the like. In addition, the cost that is incurred in creating semiconductor packages may have a significant impact on the package that is used. For this reason, universality of the package, whereby the package can be used to package a variety of different semiconductor devices, is a desired objective. In addition and most importantly, the package must be of a nature where the package protects the packaged device from the environment.
The Thermal Coefficient of Expansion (TCE) that is in force for both the semiconductor device and the package in which the semiconductor device is mounted must be such that no undue thermal stress is exerted on the device or any of its components such as contact balls or solder bumps. With increasing temperature, the semiconductor device expands as do the surrounding components of leadframe (molded plastic based, TAB based or other) and the main body of the package. If the relative expansion of these components differs considerably, a great amount of stress may be introduced at the points where the semiconductor device interfaces with the package, typically solder balls or solder bumps. This stress can lead to solder ball fatigue and eventual damage to or destruction of the solder ball.
It has already been pointed out that many of the considerations that go into the design of a semiconductor package are driven by I/O availability. For this reason, many of the device packages have the bond pads located along the periphery of the die which allows for an increase in the number of I/O connections that can be established to the package. In addition, the Ball Gird Array device further enhances the availability of the number of I/O connections for a package. The number of I/O points that can be connected to a package is further enhanced if the contact pads (bond pads) that are used for the I/O interconnects are reduced in size. Reliability considerations however limit the reduction that can be applied to the size of the bond pads.
Many of the electrical performance parameters are determined by the length of the path that electrical signals have to travel over interconnects, including bond pads and I/O's. In general, the shorter the path that is traveled, the less the impact of resistive voltage drop and parasitic capacitance. Special arrangements are therefore frequently made to shorten the paths that signals have to travel inside a package, one of these arrangements is the creation of a bond pad buffer zone that serves as the interface between the semiconductor die and the bond pads that interconnect the die.
U.S. Pat. No. 5,172,471 (Huang) shows a die with standard pads.
U.S. Pat. No. 5,567,655 (Rostoker et al.) shows a zig-zag layout of I/O pads.
U.S. Pat. No. 6,060,683 (Estrada) shows a process to remove a dielectric layer over a panel. However, this reference differs from the present invention.